The disclosed subject matter relates generally to integrated circuit devices and, more particularly, to a level shifter with primary and secondary pull-up circuits.
Modern integrated circuit (IC) devices often have to interface with IC devices from previous technology generations. However, the complementary metal-oxide semiconductor (CMOS) voltage levels on IC devices from previous technology generations are usually different from those on IC devices from the current technology generation. Also, modern CMOS “System on a Chip” (SOC) devices employ several different voltages on the same IC device. Thus, to provide proper interfacing between different CMOS voltage levels, modern IC devices typically include input/output (I/O) buffers that are capable of driving voltages greater or less than the source voltage. Also, in modern IC devices, clock-generation circuitry (e.g., phase locked loops) and the primary logic are in different voltage domains. Thus, the primary logic clocks have to be level-shifted between different voltage domains. To address these I/O buffer or voltage domain issues, a level shifter may be employed to allow the changing of the signal voltage. For a level-shifter used to level-shift clock signals, not only do the voltage-shifting characteristics need to be robust, but also the duty cycle and the delay need to be addressed.
In general, a level shifter is coupled to a power supply having a voltage different from the source voltage. In response to the values of the input signals, the level shifter circuit uses a set of output drivers to provide output voltages corresponding to the power supply voltage. For example, a level shifter may receive input signals ranging from 0 V to 0.7 V and provide output signals ranging from 0 V to 3.3 V, accordingly.
Typically, a level shifter includes a first output stage (OUT) for providing a logic output having the same logic state as the differential input signal and a complimentary output stage (OUTX) having a complimentary logic state compared to the differential input signal. A level shifter typically uses differently sized pull-up and pull-down transistors to improve writeability. For example, the N-type pull-down transistor that receives the input signal is typically larger than the P-type pull-up transistor used at the output. As a result, the rise time for the level shifter is typically faster than the fall time, introducing a skew between the OUT and OUTX outputs of the level shifter.
This section of this document is intended to introduce various aspects of art that may be related to various aspects of the disclosed subject matter described and/or claimed below. This section provides background information to facilitate a better understanding of the various aspects of the disclosed subject matter. It should be understood that the statements in this section of this document are to be read in this light, and not as admissions of prior art. The disclosed subject matter is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.